Technical Field
The present disclosure relates to a semiconductor device and a semiconductor device manufacturing method.
Related Art
Japanese Patent Application Laid-Open (JP-A) No. 2004-288725 discloses a manufacturing method for a semiconductor device in a Wafer Level Chip Size Package (WL-CSP). In this semiconductor device manufacturing method, first, an IC wafer is formed with bump electrodes arrayed on an active face (front face), and a support member is applied to a peripheral edge portion of the active face of the IC wafer. Moreover, a protective tape used during back grinding is applied over the support member, so as to cover the bump electrodes. In a state in which the active face is protected by the protective tape, a non-active face (back face) of the IC wafer is ground by back grinding to make the thickness of the IC wafer thinner. When the back grinding has been completed, the protective tape and the support member are peeled away.
In such a semiconductor device manufacturing method, the non-active face of the IC wafer is ground in a state in which the peripheral edge portion is mechanically supported by the support member, such that cracking and chipping are not liable to occur at the peripheral edge portion of the IC wafer.
In the semiconductor device manufacturing method described above, the support member is applied to the peripheral edge portion of the IC wafer after forming the bump electrodes on the active face of the IC wafer. When the support member is being applied, there is a possibility that the support member could contact the bump electrodes and damage the bump electrodes. Moreover, in the semiconductor device manufacturing method described above, a process to apply the support member is required in addition to a process to apply the protective tape, thereby increasing the number of manufacturing processes.